Microprocessor & Microcontroller
Complete formula & architecture reference for Intel 8085 (µP) and 8051 (µC). Features interactive simulators, block diagrams, addressing modes, and interface logic.
UNIT 1 — Microprocessor Basics (8085)
1.1 Generation & Evolution Timeline
| Gen | Year | Bits | Example Processors |
|---|---|---|---|
| 1st Gen | 1971-1972 | 4-bit | Intel 4004, 4040 |
| 2nd Gen | 1974-1977 | 8-bit | Intel 8080, 8085, Zilog Z80 |
| 3rd Gen | 1978-1982 | 16-bit | Intel 8086, 8088, Zilog Z8000 |
| 4th Gen | 1985-1992 | 32-bit | Intel 80386, 80486, Motorola 68000 |
| 5th Gen | 1993-2000 | 32/64-bit | Intel Pentium I,II,III,IV |
| 6th Gen | 2003+ | 64-bit | Intel Core 2, i3/i5/i7/i9, AMD Ryzen |
| Latest | 2020+ | 64-bit | Intel Core Ultra, AMD Ryzen 9, Apple M3 |
$$ \text{Moore's Law:} \quad \text{Transistor count
doubles} \approx \text{every 2 years} $$
- Intel 4004 (1971): 2300 transistors @ 108 kHz
- Intel Core i9 (Modern): ~26 billion transistors @ ~6.0 GHz
- Data bus: 4-bit $\rightarrow$ 64-bit
- Address bus: 12-bit $\rightarrow$ 64-bit
1.2 Intel 8085 Architecture & Bus Structure
$$ \text{Address Bus: 16-bit (unidirectional)} $$
$$ \text{Memory addressable: } 2^{16} = 65536 =
64\text{KB} $$
$$ \text{Data Bus: 8-bit (bidirectional)} $$
$$ \text{Control Bus: } \overline{RD}, \overline{WR},
ALE, IO/\overline{M} $$
Multiplexed Lower Address Bus
$$ AD_0 - AD_7 = \text{Address (A0-A7) or Data
(D0-D7)} $$
$$ \text{ALE = 1} \rightarrow \text{Address on
AD0-AD7} $$
$$ \text{ALE = 0} \rightarrow \text{Data on AD0-AD7}
$$
Hover over an architectural block to see details.
1.3 Arithmetic Logic Unit (ALU) & Flags
- Arithmetic: ADD, SUB, INR, DCR, DAA
- Logical: ANA, ORA, XRA, CMA, CMC
- Rotate: RLC, RRC, RAL, RAR
Flag Register (F)
S
Z
X
AC
X
P
X
CY
$$ S = 1 \text{ if result MSB = 1 (negative)} $$
$$ Z = 1 \text{ if result = 00H (zero)} $$
$$ AC = 1 \text{ if carry from bit 3 to bit 4} $$
$$ P = 1 \text{ if number of 1s in result is even} $$
$$ CY = 1 \text{ if carry from bit 7 (overflow)} $$
2's Complement Subtraction
$$ A - B = A + \text{(2's complement of B)} $$
$$ \text{2's comp} = \overline{B} \text{ (1's comp)} + 1 $$
1.4 Register Organization
- Accumulator (A): 8-bit, main working register
- General Purpose: B, C, D, E, H, L (6 x 8-bit)
- Register Pairs: BC, DE, HL (16-bit pairs)
- Stack Pointer (SP): 16-bit, points to stack top
- Program Counter (PC): 16-bit, next instruction
Interactive Register File
1.5 8085 Interrupts
| Interrupt | Priority | Type | Vector Addr | Maskable? |
|---|---|---|---|---|
| TRAP | 1 (High) | Edge/Level | 0024H | No |
| RST 7.5 | 2 | Edge | 003CH | Yes |
| RST 6.5 | 3 | Level | 0034H | Yes |
| RST 5.5 | 4 | Level | 002CH | Yes |
| INTR | 5 (Low) | Level | Ext (8259) | Yes |
$$ RST\,n \rightarrow \text{Address} = n \times 8
\text{ (in hex)} $$
SIM (Set Interrupt Mask) Bit Pattern
SOD
SOE
X
R7.5
MSE
M7.5
M6.5
M5.5
RIM (Read Interrupt Mask) Bit Pattern
SID
I7.5
I6.5
I5.5
IE
M7.5
M6.5
M5.5
1.6 8085 Pin Description (40-pin DIP)
Hover over a pin to view its function.
1.7 Machine & Instruction Cycles
$$ T = \frac{1}{f_{clock}} \quad (f_{max} = 3\text{MHz})
$$
$$ T_{instruction} = \sum T_{machine\_cycles} $$
$$ \text{Execution Time} = N_{T-states} \times T_{clock}
$$
- Opcode Fetch (M1): 4 to 6 T-states
- Memory Read/Write: 3 T-states
- I/O Read/Write: 3 T-states
- Example (MVI A, 3EH): M1(4) + M2(3) = 7 T-states
- Example (STA 2050H): M1(4) + M2(3) + M3(3) + M4(3) = 13 T-states
Timing for Opcode Fetch (M1)
UNIT 2 — Microprocessor Programming (8085)
2.1 Instruction Set & Word Size
Instruction Word Sizes
- 1-Byte Instruction: Opcode only. Example:
MOVA, B(78H) - 2-Byte Instruction: Opcode + 8-bit Data/Address. Example:
MVIA, 32H(3EH 32H) - 3-Byte Instruction: Opcode + 16-bit Address. Example:
LDA2050H(3AH 50H 20H)
Classification of Instructions
| Group | Function | Examples |
|---|---|---|
| Data Transfer | Copy data (no flags affected) | MOV, MVI, LDA, STA, LXI, XCHG |
| Arithmetic | Math ops (affects flags) | ADD, SUB, INR, DCR, DAA |
| Logical | Boolean ops, rotates | ANA, ORA, XRA, CMP, RLC, RAR |
| Branching | Change execution flow | JMP, JZ, JC, CALL, RET |
| Machine Control | Halt, interrupt, stack ops | HLT, NOP, PUSH, POP, EI, DI |
; Subroutine to Multiply 8-bit numbers in B and C
; Result stored in HL pair
MULT: LXI H, 0000H ; Clear HL
(Product = 0)
MOV A, C ; Move multiplier to A
CPI 00H ; Check if multiplier is 0
JZ END ; If 0, result is 0
LOOP: DAD B ; HL = HL + BC (Add
multiplicand)
DCR A ; Decrement multiplier
JNZ LOOP ; Repeat until A = 0
END: RET ; Return to caller
2.2 8085 Addressing Modes
Immediate Addressing: Data is provided directly in the instruction
itself. Ex: MVI A, 45H.
2.3 Interactive 8085 Program Executor (Addition)
MVI A, 05H ; Load A with
05H
MVI B, 03H ; Load B with
03H
ADD B ; Add B to A (A = A
+ B)
STA 2050H ; Store A into
memory 2050H
HLT ; Halt execution
Accumulator (A)
00H
Register B
00H
Flags (Z, CY)
Z=0, CY=0
Memory [2050H]
00H
UNIT 3 — Microprocessor Applications
3.1 Interfacing ADC & DAC
Digital to Analog Converter (DAC 0808)
- Converts 8-bit digital input to analog current output.
- Usually employs an R-2R ladder network.
$$ V_{out} = V_{ref} \times \left( \frac{D_7}{2} + \frac{D_6}{4} + ... +
\frac{D_0}{256} \right) $$
Analog to Digital Converter (ADC 0809)
- Successive Approximation Register (SAR) type.
- Requires START (SOC) and End of Conversion (EOC) signals.
Interactive 8-bit DAC Simulator
Input
(Hex): 00H
Vout:
0.00 V
Assumes
Vref = 5V. Click bits to toggle.
3.2 8255 Programmable Peripheral Interface
The 8255 provides three 8-bit I/O ports (Port A, Port B, Port C). It operates in various modes determined by the Control Word.
| Mode | Description |
|---|---|
| BSR Mode | Configures individual pins of Port C (Set/Reset). |
| I/O Mode 0 | Simple Input/Output for Ports A, B, C. |
| I/O Mode 1 | Handshake I/O (Strobed I/O). |
| I/O Mode 2 | Bidirectional Data Bus (Port A only). |
Control Word Format (I/O Mode)
D7
1
1
D6
Mdl(A)
Mdl(A)
D5
Md(A)
Md(A)
D4
PA
PA
D3
PC(Up)
PC(Up)
D2
Md(B)
Md(B)
D1
PB
PB
D0
PC(Lo)
PC(Lo)
- D7 = 1 (I/O Mode active).
- D6, D5: Port A Mode (00=0, 01=1, 1x=2).
- D4, D1, D3, D0: Port Direction (1=Input, 0=Output).
- D2: Port B Mode (0=0, 1=1).
3.3 Waveform Generation & Measurement
Square Wave Generation
By continuously writing alternatiing high (FFH) and low (00H) values to a DAC via 8255 with a delay, a square wave is produced.
START: MVI A, FFH
OUT PORT_DAC
CALL DELAY
MVI A, 00H
OUT PORT_DAC
CALL DELAY
JMP START
Oscilloscope Output
3.4 Stepper & DC Motor Control
Stepper Motor Sequence (Full Step)
To rotate a 4-coil stepper, energize coils in a specific sequence using an output port.
Step 1: 09H
Step 2: 0CH
Step 3: 06H
Step 4: 03H
DC Motor Speed Control (PWM)
$$ \text{Speed} \propto \text{Average Voltage} = V_{in} \times \left(
\frac{T_{ON}}{T_{ON} + T_{OFF}} \right) $$
UNIT 4 — Microcontroller Basics (8051)
4.1 Microprocessor vs Microcontroller
| Feature | Microprocessor (MPU) | Microcontroller (MCU) |
|---|---|---|
| Components | CPU only. Memory, I/O, timers must be added externally. | CPU + RAM + ROM + I/O + Timers on a single chip. |
| Application | General-purpose systems (PCs, laptops). | Application-specific systems (Washing machines, ACs). |
| Cost & Size | Higher cost, larger PCB size. | Lower cost, compact size. |
| Power Consumption | High power consumption. | Low power consumption (ideal for batteries). |
4.2 Architecture of 8051 (Harvard Architecture)
8051 Key Features
- 8-bit ALU, Accumulator, and 8-bit Registers.
- 16-bit Program Counter (PC) and Data Pointer (DPTR).
- 4 KB On-chip ROM (Program Memory).
- 128 Bytes On-chip RAM (Data Memory).
- Four 8-bit I/O Ports (P0, P1, P2, P3).
- Two 16-bit Timers/Counters (T0, T1).
- Full-duplex serial port (UART).
Hover over an architectural block to see details.
4.3 RAM Organization & Special Function Registers (SFRs)
Internal 128-Byte RAM (00H - 7FH)
Program Status Word (PSW)
The PSW is an 8-bit SFR at address D0H. It contains status flags and register bank selection bits.
CY
AC
F0
RS1
RS0
OV
—
P
| RS1 | RS0 | Selected Bank | Address |
|---|---|---|---|
| 0 | 0 | Bank 0 | 00H - 07H |
| 0 | 1 | Bank 1 | 08H - 0FH |
| 1 | 0 | Bank 2 | 10H - 17H |
| 1 | 1 | Bank 3 | 18H - 1FH |
UNIT 5 — 8051 Addressing Modes & Instructions
5.1 Addressing Modes of 8051
| Mode | Syntax | Description |
|---|---|---|
| Immediate | #data |
Data is specified in the instruction. Ex:
MOV A, #55H
|
| Register | Rn or A |
Operand is in a register (R0-R7, A). Ex:
MOV A, R1
|
| Direct | address |
8-bit internal RAM address given. Ex:
MOV 50H, A (Move A to RAM 50H)
|
| Register Indirect | @Ri |
Address is held in R0 or R1. Ex:
MOV A, @R0
|
| Indexed | @A+DPTR |
Accesses lookup tables in ROM. Ex:
MOVC A, @A+DPTR
|
| Bit Addr. | bit |
Operates on a single bit. Ex:
SETB P1.0
|
Interactive Indexed Addressing (MOVC)
Indexed addressing is widely used to retrieve values from ROM lookup tables, such as 7-segment display codes.
DPTR: 0300H
A (Offset): 00H
Computed Addr:
@A+DPTR = 0300H
ROM
Data lookup:
3FH (Digit '0')
5.2 8051 Assembly Programs
Addition of Two 8-bit Numbers
- Load numbers into A and B.
- Add. Store result and save carry.
; Load data
MOV A, #55H
MOV B, #0A5H
; R0 holds carry
MOV R0, #00H
; Add B to A
ADD A, B
JNC SKIP ; Jump if No Carry
INC R0 ; Increment R0 if Carry=1
SKIP: MOV 50H, A ; Store sum in mem
50H
MOV 51H, R0
; Store carry in mem 51H
SJMP $ ; Halt (Short Jump to Self)
Data Transfer (Block Move)
- Move 10 bytes from SRC (30H) to DST (40H).
MOV R0, #30H
; Source pointer
MOV R1, #40H
; Dest pointer
MOV R2, #0AH
; Counter (10 bytes)
BACK: MOV A, @R0 ; Read from
Source
MOV @R1, A
; Write to Dest
INC R0 ; Adv Source PTR
INC R1 ; Adv Dest PTR
DJNZ R2, BACK
; Decrement R2, jump if not 0
SJMP $ ; Done
UNIT 6 — 8051 Interrupts & Timers
6.1 8051 Interrupt System
The 8051 has 5 interrupt sources. The Interrupt Enable (IE) and Interrupt Priority (IP) SFRs control them.
| Interrupt | Flag | Vector Addr. | Priority* |
|---|---|---|---|
| External 0 (INT0) | IE0 | 0003H |
1 (Highest) |
| Timer 0 (TF0) | TF0 | 000BH |
2 |
| External 1 (INT1) | IE1 | 0013H |
3 |
| Timer 1 (TF1) | TF1 | 001BH |
4 |
| Serial (RI / TI) | RI/TI | 0023H |
5 (Lowest) |
*Default polling sequence
if IP is not set.
Interrupt Enable (IE) Register
EA
(D7)
(D7)
—
(D6)
(D6)
ET2
(D5)
(D5)
ES
(D4)
(D4)
ET1
(D3)
(D3)
EX1
(D2)
(D2)
ET0
(D1)
(D1)
EX0
(D0)
(D0)
Enable All (EA) bit must be 1 for any generic interrupt to trigger.
Interrupt Priority (IP) Logic
Setting an IP bit to '1' makes it a high priority interrupt. High priority interrupts can break into low priority ISRs.
6.2 Timers and Counters (TMOD & TCON)
Timer Modes (TMOD)
- Mode 0: 13-bit Timer (rarely used).
- Mode 1: 16-bit Timer (counts 0000H to FFFFH).
- Mode 2: 8-bit Auto-Reload Timer (TH auto-loads into TL upon overflow).
- Mode 3: Split Timer (Timer 0 only).
Timer Delay Calculation
Assuming Crystal Freq = 11.0592 MHz, Machine Cycle Freq = $\frac{11.0592}{12} = 921.6$ kHz.
$$ \text{Clock Period} (T_{cycle}) = \frac{1}{921.6 \text{ kHz}} \approx 1.085 \mu s
$$
$$ \text{Delay} = \text{Count} \times T_{cycle} $$
Mode 1 (16-bit) Count Calculator
Clock Cycles needed:
46083
65536 - count =
Initial:
19453
Hex Values:
TH
= 4BH | TL = FDH
UNIT 7 — Application of Microcontroller
7.1 Motor Speed Control (PWM via Timers)
Pulse Width Modulation
By rapidly switching a pin HIGH and LOW using 8051 timers, we constrain the average voltage seen by a DC motor, controlling its speed.
$$ V_{avg} = V_{in} \times \text{Duty Cycle} $$
$$ \text{Duty Cycle (\%)} = \left( \frac{T_{ON}}{T_{ON} + T_{OFF}} \right) \times
100 $$
Implementation
- Setup Timer 0 to generate a fixed frequency interrupt (e.g., 10kHz).
- Maintain a software counter (0-100) inside the ISR.
- If Counter < DutyCycle, Set Motor Pin=1. Else, Motor Pin=0.
DC Motor Simulator (PWM)
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